1. Field
Example embodiments relate to a non-volatile memory device and methods of manufacturing and operating the non-volatile memory device. Other example embodiments relate to a non-volatile memory device including a split gate and methods of manufacturing and operating the non-volatile memory device.
2. Description of the Related Art
Generally, a semiconductor memory device is classified into a volatile memory device, e.g., a dynamic random access memory (DRAM) and/or a static random access memory (SRAM), which loses data over time, and a non-volatile memory device, e.g., a read only memory (ROM), that continuously stores data regardless of passage of time. The volatile memory device may rapidly input/output data. In contrast, the non-volatile memory device may slowly input/output data.
An electrically erasable programmable read only memory (EEPROM) device or a flash memory device capable of inputting/outputting data in the non-volatile memory device has been widely used. The flash memory device may electrically control an input/output of data using Fowler-Nordheim (F-N) tunneling or channel hot electron injection. A stacked gate type non-volatile memory device may have a gate structure that may include a tunnel insulation layer, a floating gate electrode, a dielectric layer and a control gate electrode sequentially stacked on a semiconductor substrate, e.g., a silicon wafer.
A split gate type non-volatile memory device may have a split gate structure that may include a gate insulation layer formed on a semiconductor substrate, a floating gate electrode formed on the gate insulation layer, an oxide layer pattern formed on the floating gate electrode, a tunnel oxide layer formed on a sidewall of the floating gate electrode, and a control gate electrode formed on the tunnel oxide layer. FIG. 1 is a cross-sectional view illustrating a conventional split gate type non-volatile memory device. Referring to FIG. 1, a gate insulation layer 106 may be formed on a semiconductor substrate 100 having source/drain regions 102 and 104. A floating gate electrode 108 may be formed on the gate insulation layer 106. A concave recess may be formed on a surface portion of the floating gate electrode 108. A dielectric layer 112 surrounds a sidewall of the floating gate electrode. Further, a control gate electrode 114 is formed on the dielectric layer 112.
An oxide layer pattern 110 may be formed in the concave recess. The floating gate electrode 108 may have both tips making contact with the oxide layer pattern 110. Electrons may pass through the tips by F-N tunneling to perform a programming operation and/or an erasing operation. An integration degree of the non-volatile memory device has improved. Because the conventional split gate type non-volatile memory device is relatively large, there exists a limit to improve the integration degree of the split gate type non-volatile memory device.